1. Field of the Invention
The present invention relates to a method of fabricating a memory cell with a transistor, and more particularly, to a method of forming a dynamic random access memory (DRAM) cell having a single sided buried strap.
2. Description of the Related Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor formed in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the bottom storage electrodes of the adjacent capacitor, which forms a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, MOSFET size has been continuously reduced so that the packing density of DRAM devices has increased considerably. For example, new techniques for manufacturing extremely small transistor elements have been developed for 1 Giga bit DRAMs and beyond. One of the methods of increasing integration is to form a three-dimensional transistor structure, instead of the commonly used planar-type transistor.
FIGS. 1A through 1H are schematic sectional views showing a partially fabricated integrated circuit structure at successive stages in forming a transistor of a DRAM cell of the prior art.
In FIG. 1A, a patterned pad layer 110 is formed on a silicon substrate 100. The pad layer 110 can comprise an oxide pad layer (not shown) and a pad nitride layer (not shown). Using the pad layer 110 as a mask, a deep trench 112 is then defined in the substrate 100 by photolithography and etching. A trench capacitor (not shown) is formed in the lower portion of the deep trench 112 by a conventional process.
In FIG. 1B, a collar oxide layer 114 is formed on the sidewall of the upper portion of the deep trench 112. The collar oxide layer 114 is located above the trench capacitor (not shown). A polysilicon layer 116 is then formed filling the deep trench 112.
In FIG. 1C, the polysilicon layer 116 is etched back until the surface of a remaining polysilicon layer 116′ is lower than the surface of the substrate 100.
In FIG. 1D, by performing an etch-back process, the collar oxide layer 114 over the top surface of the remaining polysilicon layer 116′ is over-etched until the top surface of a remaining collar oxide layer 114′ is lower than that of the remaining polysilicon layer 116′. Thus, an opening 118 is formed.
In FIG. 1E, a doped polysilicon layer (e.g. a P or As doped polysilicon layer, not shown) is deposited on the pad layer 110 and fills the opening 118. Then, the doped polysilicon layer (not shown) is etched back to form a buried strap 120 at the bottom of the opening 118.
In FIG. 1F, an insulating layer (not shown) is formed to fill the opening 118. Then, the insulating layer (not shown) is partially etched back to form an insulating layer 122 on the buried strap 120.
In FIG. 1G, a gate oxide layer 124 is formed on the sidewall of the opening 118 by thermal oxidation. A gate 126 is then formed on the insulating layer 122.
In FIG. 1H, an insulating spacer 128 is formed on the sidewall of the upper portion of the opening 118. The opening 118 is then filled with conductive material to form a conductive layer 130. Next, a shallow trench isolation (STI) 132 is formed in the substrate 100 to define active areas. The pad layer 110 is then removed by CMP (chemical mechanical polishing) to obtain a smooth substrate 100 surface.
In FIG. 1H, a word line 134 is formed on the conductive layer 130. A drain region 136 is formed by using the word line 134 as a mask and implanting impurities into the substrate 100. Due to the high temperature during the mentioned manufacturing processes, impurities contained in the buried strap 120 out-diffuse into the substrate 100 to form a source region 138, as show in FIGS. 1G and 1H.
With reference to FIG. 1H, the source region 138 formed by the conventional method is circular, and the distance “d” between adjacent source regions 138, and 138 is shortened when DRAM cells are scaled down. The gap created between adjacent source regions causes a serious leakage problem (also referred to as a buried strap mergence issue), reducing device reliability.
In U.S. Pat. No. 6,432,774, Heo et al disclose a method of fabricating a DRAM cell having a vertical transistor. Though this method can form a memory cell with a single sided source region, the source region of the memory cell nevertheless faces an adjacent memory cell. Thus, the leakage problem occurs when the design rule is below 0.11 μm.
In U.S. Pat. No. 5,519,236, Ozaki discloses a DRAM cell having a vertical transistor. The method removes an oxide layer on one side by photolithography using a photoresist layer as a mask. A memory cell with a single sided source region can thus be formed. Nevertheless, this method suffers from misalignment issue during photolithography, making it unsuitable suitable for use in the narrower trench process.